Voltage regulator and data path for a memory device

ABSTRACT

One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus to a plurality of output blocks. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator. Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration. A plurality of delay circuits receives the control pulse and produces a plurality of delayed control pulses. A second logic gate receives the control pulse and the plurality of delayed control pulses and produces a control pulse of extended duration. The control pulse of extended duration may be used, for example, for temporarily sourcing additional current to an output terminal of the voltage regulator. According to another aspect of the present invention, a method is disclosed of forcing a voltage regulator into a low power mode. Another aspect of the present invention is directed to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output amplifier. The signal is then used to enable certain of the output stages in each of the output paths.

FIELD OF THE INVENTION

[0001] The present invention is directed to memory devices generally and, more particularly, to voltage regulators and data paths used in such devices.

DESCRIPTION OF THE BACKGROUND

[0002] Solid state memory devices communicate with the outside world through input/output pads. Some pads may be connected to an address bus and are thus dedicated to receiving address information. Other pads may be connected to a command bus from which command signals are received while still other pads are connected to a data bus, on which data to be written into the memory is received or data read from the memory is output. In other types of devices, the pads may be connected to a single multiplexed bus which, at one point in time outputs address and command information and, at another point in time, outputs or receives data.

[0003] To enable pads to receive or send information, the information is transmitted in the form of ones and zeros. The “ones” and “zeros” are typically represented by two different voltage levels. For example, a voltage between two and five and one half volts may be considered to represent a high signal, or a “one”, while a voltage level of between minus .3 volts and plus .8 volts may be considered to represent a low signal, or a “zero”. The output pads must be capable of reliably producing voltages within the ranges designated as representing ones and zeroes in accordance with timing specifications set for the component.

[0004] Timing specifications are typically set by the consumers of the memory devices for particular applications. A timing specification would identify how long it may take for an output pad to change from a zero to a one, e.g. change from minus .3 volts to plus five volts, how abrupt the changes must be, etc. With access times for memory devices measured in nanoseconds, it is clear the design engineer is faced with quite a challenge to design electrical circuits which can change the voltage available at the output pads so quickly.

[0005] Output pads typically are serviced by a number of circuits such as circuits for buffering (holding) data, and drive circuits for driving the voltage on the pad to a voltage representative of data to be output. The drive circuit, in turn, is serviced by devices such as voltage generators and voltage regulators which provide the power needed by the output pad drivers. The voltage regulator is used to provide power, in the form of voltage for driving the gate of an output transistor ultimately servicing an output pad. Typically, voltage regulators supply that gate voltage (Vgate) to a number of drive transistors through a voltage bus.

[0006] When the gate voltage is heavily loaded, the Vgate level recovery may not be sufficiently quick. Prior art attempts at solving this problem apply a one-shot pulse to an enable Vgate line. However, because the path between Vgate and the enable Vgate line is through a p-channel transistor with its n-well biased to Vgate, there is a risk of forward biasing the drain of the p-channel to the n-well if the one-shot pulling the enable V-gate line towards system voltage (V_(DD)) is not timed properly across all process and device conditions. Additionally, if the one-shot timing is too weak under particular process and device conditions, then Vgate will droop, and the enable Vgate lines will not recover sufficiently quickly.

[0007] Another problem is experienced in the prior art when the memory device, and hence the voltage regulator, must go into a nap or a standby mode. In such modes, the Vgate regulator needs to go to a low power mode very quickly. In some prior art configurations, that is accomplished by reducing the bias voltage supplied to an amplifier within the voltage regulator. However, simply reducing the bias voltage may not reduce the power consumption of the voltage regulator sufficiently quickly.

[0008] Another problem is encountered because output transistors typically have an RC time constant associated therewith as a result of their loading. The RC time constant prevents the output transistor from reducing its drive sufficiently quickly. In the prior art, a pass gate is used to disconnect the RC so that the output transistor can respond more quickly. However, that approach leaves one side of the RC load floating. Due to n-plus junctions, the floating side can move to a back bias voltage. Should that occur, when the RC is reconnected to the transistor, the transistor would be turned on hard.

[0009] Other problems associated with the data path relate to the output slew of data pad drivers. In the prior art, output slew rates are improved by segmenting the output transistors into two main portions and delaying the switching of one of the portions. The delay is controlled by a circuit that makes a determination as to the strength of the p- and n-channel transistors and generates a two-bit binary code. In addition to setting the delay based on the two-bit code, a NAND gate is used to receive the two-bit signal which, in turn, enables a p-channel transistor to further enable two other p-channel transistors in the output pre-driver so that they could strengthen the high side out of the pre-driver for both the normal and delayed paths. However, various changes over process and device conditions can cause the output's timing characteristic to be skewed. Because the prior art solution enables only the addition of p-channel transistors in one of the two-bit code cases, the degrees of freedom to compensate for various types of skew are limited.

[0010] Thus, the need exists for a voltage regulator and data path with improved performance characteristics.

SUMMARY OF THE PRESENT INVENTION

[0011] One aspect of the present invention is directed to a method and apparatus of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, with the gate voltages being supplied by a voltage regulator through an output bus. The demand for gate voltage is periodically determined and, when the demand is high, each line of the bus may be momentarily connected to a voltage source. In addition, additional current is temporarily sourced to the output terminal of the voltage regulator.

[0012] Another aspect of the present invention is directed to a method and apparatus of producing a control pulse of an extended duration for use in the voltage regulator having its output terminal connected to a voltage bus, and with the voltage bus serving a plurality of output to blocks through a plurality of output lines. A first logic gate receives a plurality of signals each representative of the voltage demand of one of the plurality of output blocks and produces a control pulse of a first duration. A plurality of delay circuits receives the control pulse and produces a plurality of delayed control pulses. A second logic gate receives the control pulse and the plurality of delayed control pulses and produces a control pulse of extended duration. The control pulse of extended duration may be used, for example, for temporarily sourcing additional current to an output terminal of the voltage regulator.

[0013] According to another aspect of the present invention, a method is disclosed of forcing a voltage regulator into a low power mode. The method involves increasing the rate at which a bias voltage is withdrawn from an amplifier in the voltage regulator. A node between a resistive and capacitive load connected to an output transistor of the voltage regulator is pulled to a predetermined voltage other than ground. By reducing the bias voltage, power consumption is rapidly diminished. Furthermore, by pulling the node to a predetermined voltage other than ground, the node is prevented from floating to a voltage which will turn the transistor on hard when reconnected.

[0014] Another aspect of the present invention is directed to a pre-driver or the like which provides variable output drive capability. The pre-driver is comprised of two paths each divided into output stages. A two-bit signal is generated in response to determining the relative strength of the n-channel and p-channel transistors in a subsequent output amplifier. The two-bit signal is then used to enable certain of the output stages in each of the output paths.

[0015] The present invention solves the problems encountered in prior art voltage regulators used in memory devices or other types of demanding applications. For example, the present invention insures that the power provided by the voltage regulator is adequate even under heavy load conditions. The present invention insures that the power consumption is quickly reduced when the device is put into a nap or standby mode while at the same time insuring that the device will properly power up when desired. The present invention also improves the performance of the data path. Those, and other advantages and benefits, will become apparent from the Description of the Preferred Embodiment hereinbelow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For the present invention to be easily understood and readily practiced, the present invention will now be described, for purposes of illustration and not limitation, in conjunction with the following figures wherein:

[0017]FIG. 1 is a block diagram of a memory device illustrating a voltage regulator servicing a number of output blocks;

[0018]FIG. 2 is a circuit diagram of an output block of FIG. 1;

[0019]FIG. 3 is a circuit diagram illustrating one implementation of a voltage regulator constructed according to the teachings of the present invention;

[0020]FIG. 4 is a circuit diagram of control circuit used in conjunction with the voltage regulator of FIG. 3;

[0021]FIG. 5 is a circuit diagram of a circuit for controlling the decrease in bias voltage supplied to the differential amplifier of FIG. 3;

[0022]FIG. 6 illustrates an implementation for the output transistors of a data pre-driver or the like; and

[0023]FIG. 7 is a block diagram of a computer system in which the memory device of FIG. 1 may be used.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0024] The present invention will now be described in conjunction with FIG. 1 which illustrates a memory device 10. The reader will understand the description of the present invention in conjunction with the memory 10 of FIG. 1 is merely for purposes of providing one example of an application for the present invention. The present invention is not to be limited to the application shown in FIG. 1.

[0025] The memory device 10, includes an array 12 of memory cells. The memory cells 12 are arranged in rows and columns as is known in the art. Individual cells in the array 12 may be selected for a read or write operation by row decode circuitry 14 and column decode circuitry 16 which operates in response to command information on a command bus 18 and address information on an address bus 20. Signals appearing on the command bus 18 may include, but are not limited to, chip select, row address strobe, column address strobe, write enable and clock enable. Sense amps 22 read information out of and write information into cells which have been selected by row decode circuitry 14 and column decode circuitry 16 in response to read and write commands, respectively.

[0026] The sense amps 22 form part of a data path shown generally by reference numeral 24. The data path 24 is the path along which data flows between a data bus 26 and the array 12. For a inbound data (data to be written into array 12), the data path begins at data pads 28 and ends with sense amps 22 writing the data into the array 12. For outbound data (data read from array 12), the path begins with the sense amps reading the data from the array 12 and ends with the data being output on the data pads 28.

[0027] The data path 24 is comprised of a number of circuits for buffering and amplifying the data which are not shown as they do not form a part of the present invention. A plurality of output blocks 30 is arranged such that each output block 30 services one of the data pads 28. An example of a typical output block 30 is illustrated in FIG. 2. In FIG. 2, the output block 30 is comprised of a first plurality of enable transistors 31, each connected in series with a drive transistor 32. The transistors 31 each receive the data signal q, while each of the drive transistors receives one of the Vgate enable signal EnVg<0>, EnVg<1> . . . EnVg<6>. The output block is further comprised of a second plurality of enable transistors 33, each connected in series with a drive transistor 32. The first and second pluralities of enable transistors 31, 33, respectively, must be fully turned on by the signals q and q1 for the drive transistors 32 to provide the proper pull-down load to the data pad 28 that it is servicing so that the voltage level necessary to represent the data being transferred is quickly reached. Each of the other output blocks 30 may be identically constructed, and each receives the data signals q and q1 and Vgate enable signals EnVg<0> through <6>.

[0028] Each of the lines carrying the Vgate enable signals EnVg<0> through <6>is connected to a system voltage, V_(DD), through a p-channel transistor 34. The gate of each of the transistors 34 is connected to a control circuit 36 through an inverter 38. The transistors 34 thus provide a plurality of switches which, under the control of control circuit 36, may momentarily connect the lines carrying the Vgate enable signals to the voltage source V_(DD).

[0029] Completing the description of FIG. 1, a voltage regulator 40 provides the voltage for the Vgate enable signals through Vgate enable control 41. Vgate enable control 41 provides the Vgate enable signals to the output blocks 30 through a bus 42. The bus 42 is comprised of a plurality of lines each carrying one of the Vgate enable signals EnVg<0> through <6>.

[0030] Turning now to FIG. 3, a circuit diagram illustrating one implementation of the voltage regulator 40 constructed according to the present invention is illustrated. The voltage regulator 40 has an output terminal 44. A p-channel transistor 46 is connected between a voltage source and the output terminal 44 and an n-channel transistor 48 is connected between the output terminal 44 and ground.

[0031] A transistor 50 receives at its gate terminal, through a pass gate 52, the same signal (OUT 1) that the transistor 46 receives. The pass gate 52 is operative in response to a boost signal produced by the control circuit 36. The boost signal is also input to a gate terminal of a p-channel transistor 54 through an inverter 56. The p-channel transistor 54 is connected across a gate terminal of the p-channel transistor 50 and a voltage source.

[0032] In FIG. 4, a circuit diagram of a control circuit 36 which may be used in conjunction with the voltage regulator of FIG. 3 is illustrated. In FIG. 4, a plurality of one-shot multivibrators 56 is provided. Each of the one-shots is triggered if its corresponding Vgate enable signal is enabled through Vgate enable control 41. An exemplary embodiment for one of the one-shots 56 is illustrated at 56′. One-shot 56′ receives a signal <6> indicative of the need to enable the Vgate enable signal EnVg<6>. When the signal <6> indicates the need to enable the signal EnVg<6>, and an enable signal V-GCC₁₃ EN is present, the one-shot 56′ produces an output pulse 58. The output pulse 58 is input to the transistor 34 through the inverter 38 shown in FIG. 1 to momentarily render the p-channel transistor 34 conductive. In that manner, the line carrying the signal EnVg<6> is momentarily connected to the voltage source V_(DD), with the time of connection being determined by the width of the pulse 58. The other one-shots 56 are similarly constructed and used to momentarily connect the other lines carrying the Vgate enable signals to the voltage source V_(DD).

[0033] NOR gates 60, 61 and 62 are used to aggregate the pulses produced by the one-shots 56. The outputs of the NOR gates are input to a first logic gate 64 which is a NAND gate. The output of the NAND gate 64 is connected to an input of a second gate which is a NOR gate 66. The output of the NAND gate 64 is also connected to a second input of the NOR gate 66 through a delay circuit 68. The output of the delay circuit 68 is connected to another input of the NOR gate 66 through a second delay circuit 70. The boost signal described above in conjunction with FIG. 3 is available at an output terminal of the NOR gate 66. That signal may be delayed further by propagating it through a pair of inverters 71 and 72.

[0034] The operation of the circuitry described thus far will now be explained. When the Vgate signal is loaded heavily as a result of various conditions (e.g. during switching of the EnVg lines), the Vgate level at output terminal 44 in FIG. 3 may not recover sufficiently quickly. Two steps are taken to boost the voltage. The first step is to render the p-channel transistor 34 servicing the relevant line carrying the Vgate enable signal which has just been enabled momentarily conductive through use of the pulse 58. That enables the individual line carrying the particular Vgate enable signal to be momentarily connected to the voltage source V_(DD). Thus, the plurality of transistors 34 may be considered to be part of a booster circuit as their function is to momentarily boost the voltage available to the particular line carrying the Vgate enable signal which has just been enabled.

[0035] The second step which is taken is described in conjunction with FIG. 3. When the boost signal goes active low, pass gate 52 becomes conductive which renders transistor 50 conductive which gives the voltage regulator 40 much more pull-up capability. At the same time, transistor 54 is turned off. With the p-channel side of the regulator's output thus strengthened, the voltage regulator 40 has about a 20 millivolt higher Vgate regulation point. That helps Vgate hit its final value under heavy load conditions. Thus, the circuitry within the dotted box 74 may also be considered to be part of a booster circuit comprised of a transistor 50 with the remaining components comprising a control circuit for controlling the conductivity of transistor 50.

[0036] If only the p-channel side of the voltage regulator 40 is strengthened, somewhat of an offset is created because the p-channel side of the output has more current carrying capability than the n-channel side. That offset can be compensated by adding a booster circuit 75 which is similar to the circuit 74. In the booster circuit 75, the transistor 50 becomes an n-channel transistor 50′. The control portion of the booster circuit 75 is likewise changed as follows: the transistor 54 becomes an n-channel transistor 54′. The transistors 50′ and 54′ have their source and well connections to V_(ss) and V_(bb), respectively. The input to pass gate 52′ is the same signal input to the gate of transistor 48. Transistor 54′ receives the active low boost signal directly. The sizings of the various components comprising the booster circuit 75 would be such that the offset would be nulled out.

[0037] In summary, when selected Vgate enable signals are initially enabled, the booster circuit comprised of the plurality of transistors 34 is rendered operative so that one, some or all of the transistors 34 are rendered conductive to momentarily connect the line(s) carrying the Vgate enable signal(s) to a voltage source. The boost signal, produced under heavy load conditions, enables the output terminal 44 of the voltage regulator 40 to be sourced with additional current through booster circuit 74 in an unbalanced mode, or through booster circuits 74 and 75 in a balanced mode.

[0038] Production of the boost signal will now be described in conjunction with FIG. 4. In FIG. 4, the NAND gate 64 produces a control pulse whenever it receives a low going pulse at one or more of its input terminals. The NAND gate 64 will produce a control pulse whenever selected Vgate enable signals are initially enabled. Optionally, the lowest three lines, lines 2, 1 and 0 can be optioned out by a switch 76 because the capacitance on those lines is so small that Vgate is not affected much when they turn on. Obviously, the selection of other types of gates and other arrangements of gates could cause the control pulse to be produced under different conditions.

[0039] It has been found that the control pulse produced by the NAND gate 64 is not of sufficient duration. As a result, the control pulse is input directly to the second gate 66 to cause the gate 66 to change states to a low state. The control pulse is also input to the gate 66 through the delay circuit 68. In that manner, as the control pulse from gate 64 prepares to end, a delayed control pulse produced by delay circuit 68 becomes available at an input terminal of the gate 66, thereby insuring that the output of the gate 66 does not change state. In a similar manner, the delayed control pulse produced by the delay circuit 68 is input to the second gate 66 through the delay circuit 70 such that when the delayed control pulse produced by the delay circuit 68 is preparing to end, the delayed control pulse produced by the delay circuit 70 is input to an input terminal of the gate 66 thereby insuring that the output of the gate 66 does not change when the delay pulse produced by the delay circuit 68 ends. By chaining together a plurality of delay circuits 68 and 70, and producing a plurality of delayed control pulses, a control pulse of extended duration can be obtained at the output of the second gate 66. Additional delay circuits 68, 70 can be added to increase the length of the control pulse of extended duration. The control pulse of extended duration is the boost signal which is input to the control portion of the booster circuit 74.

[0040] The delay circuits 68 and 70 together with the NOR gate 66 may be viewed as a pulse extender. To insure glitch-free operation, the pulse extender of the present invention should have outputs taken from enough points along the delay line to insure no glitch in the extended pulse.

[0041] Returning to FIG. 3, the voltage regulator 40 may have a differential amplifier 78 which produces a first output signal, OUT 1, for directly driving transistor 46 and a second output signal, OUT 2, which indirectly drives transistor 48. A bias voltage is supplied to the differential amplifier 78 through an n-channel transistor 82. Transistor 82 is responsive to a control signal VgRegBias. A transistor 84 is connected in series with a transistor 85, with the two transistors 84 and 85 connected in parallel with the transistor 82. The boost signal may be additionally used to control the transistor 84. Because the boost signal is active low, an active high version is taken from the output of inverter 56, such that when the boost signal is active, the transistor 84 is turned on.

[0042] When going into nap or standby modes, the voltage regulator needs to go to a low power mode very quickly. It has been determined that the steps currently taken to reduce the bias voltage, by decreasing the control signal VgRegBias, are insufficient. As shown in FIG. 5, a one-shot 86 is responsive to a signal VgNap which is responsible for putting the voltage regulator 40 into a nap or standby mode. The one-shot 86 produces an output pulse which temporarily renders transistor 88 conductive. When the transistor 88 is conductive, a transistor 90, connected to operate as a diode, pulls the signal VgRegBias within a Vt of ground thereby causing it to decrease even more rapidly. When the single pulse produced by the one-shot 86 is no longer available, the diode 90 is no longer conductive as the transistor 88 is turned off. In that manner the reduction in bias voltage can be increased.

[0043] It has been determined that even if the voltage reduction of the signal VgRegBias occurs sufficiently quickly, a compensation resistor 92 and compensation capacitor 94, which are a load across the transistor 46, can keep the p-channel transistor 46 from reducing its drive sufficiently quickly. The pulse produced by the one-shot 86 of FIG. 5 is used to pull a node 96 between the resistor 92 and capacitor 94 to a predefined voltage other than zero through a transistor 98. In the embodiment shown in FIG. 3, the predefined voltage is V_(DD) which allows transistor 46 to go to a low power mode very quickly. This actually shuts off the transistor 46 briefly, but because that shutoff occurs at the beginning of a nap or standby mode, the shutoff is a non-issue. To avoid that brief shutoff, instead of pulling the node 96 up to V_(DD), the node 96 could be pulled up to a large p-channel diode tied to V_(DD). The p-channel diode must be sized such that it allows quick pullup while leaving transistor 46 on near steady state nap or standby conditions. That embodiment comes at a layout expense as the p-channel diode needs to be sufficiently large.

[0044] Illustrated in FIG. 6 is an output pre-driver circuit 100. The pre-driver circuit 100 is constructed of a first data path 102 responsive to a data signal Q and a second data path 104 responsive to a delayed version of the data signal Q′. The first data path 102 has two output transistor drive stages 106 and 108 while the second data path 104 similarly has two transistor output drive stages 110 and 112. The transistors 106 and 110 are enabled when a signal sl1 renders a transistor 114 conductive. The transistors 108 and 112 are operative when a signal sl2 renders a transistor 116 conductive.

[0045] It is known in the art to monitor the strength of the p-channel and n-channel transistors in an output drive device (not shown) and to generate a two-bit signal where sl1 and sl2 represent the two bits of the binary signal. The implementation of the output pre-driver 100 in FIG. 6 allows the p-channel device 106 to be rendered conductive independently of the p-channel device 108. The p-channel device 110 can be enabled independently of the p-channel transistor 112. As a result, all four transistors 106, 108, 110 and 112 may be on, transistors 106 and 110 may be on while transistors 108 and 112 may be off, and transistors 108 and 112 may be on while transistors 106 and 110 are off. With the arrangement shown in FIG. 6, three of the four two-bit codes can have different total amounts of p-channel drive enabled in the pre-driver 100. With proper tuning, more skew can be eliminated from the subsequent output driver stages with the pre-driver 100 illustrated in FIG. 6.

[0046]FIG. 7 illustrates a computer system 200 containing the memory of FIG. 1. The computer system 200 includes a processor 202 for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor 202 includes a processor bus 204 that normally includes an address bus, a control bus, and a data bus. In addition, the computer system 200 includes one or more input devices 214, such as a keyboard or a mouse, coupled to the processor 202 to allow an operator to interface with the computer system 200. Typically, the computer system 200 also includes one or more output devices 216 coupled to the processor 202, such output devices typically being a printer or a video terminal. One or more data storage devices 218 are also typically coupled to the processor 202 to allow the processor 202 to store data in or retrieve data from internal or external storage media (not shown). Examples of typical storage devices 218 include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor 202 is also typically coupled to cache memory 226, which is usually static random access memory (“SRAM”) and to an SDRAM 228 through a memory controller 230. The memory controller 230 normally includes a control bus 236 and an address bus 238 that may be coupled to the SDRAM 228. A data bus 240 may be coupled to the processor bus 204 either directly (as shown), through the memory controller 230, or by some other means.

[0047] While the present invention has been described in conjunction with preferred embodiments thereof, those of ordinary skill in the art will recognize that many modifications and variations may be made. The foregoing description and the following claims are intended to cover all such modifications and variations.

RELATED APPLICATION

[0048] This application is a division of co-pending application Ser. No. 09/654,099.

BACKGROUND

[0049] Field of the Invention

[0050] The present invention is directed to memory devices generally and, more particularly, to voltage regulators and data paths used in such devices.

[0051] Description of the Background

[0052] Solid state memory devices communicate with the outside world through input/output pads. Some pads may be connected to an address bus and are thus dedicated to receiving address information. Other pads may be connected to a command bus from which command signals are M received while still other pads are connected to a data bus, on which data to be written into the memory is received or data read from the memory is output. In other types of devices, the pads may be connected to a single multiplexed bus which, at one point in time outputs address and command information and, at another point in time, outputs or receives data.

[0053] To enable pads to receive or send information, the information is transmitted in the form of ones and zeros. The “ones” and “zeros” are typically represented by two different voltage levels. For example, a voltage between two and five and one half volts may be considered to represent a high signal, or a “one”, while a voltage level of between minus .3 volts and plus .8 volts may be considered to represent a low signal, or a “zero”. The output pads must be capable of reliably producing voltages within the ranges designated as representing ones and zeroes in accordance with timing specifications set for the component.

[0054] Timing specifications are typically set by the consumers of the memory devices for particular applications. A timing specification would identify how long it may take for an output pad to change from a zero to a one, e.g. change from minus .3 volts to plus five volts, how abrupt the changes must be, etc. With access times for memory devices measured in nanoseconds, it is clear the design engineer is faced with quite a challenge to design electrical circuits which can change the voltage available at the output pads so quickly. 

What is claimed is:
 1. A method of boosting the voltage supplied to an output pad driver through a bus connected to a voltage regulator, comprising: momentarily connecting the bus to a voltage source; and temporarily sourcing additional current to the output terminal of the voltage regulator.
 2. The method of claim 1 additionally comprising generating a one-shot control pulse, and wherein said one-shot control pulse initiates the momentarily connecting step.
 3. The method of claim 1 additionally comprising generating a temporary control pulse, and wherein said temporary control pulse initiates the temporarily sourcing step.
 4. A method of boosting the gate voltages for transistors controlling the voltage appearing on output pads of a solid state memory device, said gate voltages supplied by a voltage regulator through an output bus, comprising: periodically determining the demand for gate voltage and, when the demand is high, momentarily connecting each line of the bus to a voltage source; and temporarily sourcing additional current to the output terminal of the voltage regulator.
 5. The method of claim 4 additionally comprising generating a one-shot control pulse, and wherein said one-shot control pulse initiates the momentarily connecting step.
 6. The method of claim 4 additionally comprising generating a temporary control pulse, and wherein said temporary control pulse initiates the temporarily sourcing step.
 7. A booster circuit for use with a voltage regulator, having an output terminal coupled with a voltage bus, said voltage bus servicing a plurality of output blocks through a plurality of output lines, said booster circuit comprising: a plurality of switches for connecting each output line of the voltage bus to a voltage source; and a switching circuit for sourcing additional current to the output terminal of the voltage regulator.
 8. The booster circuit of claim 7 wherein said plurality of switches includes a plurality of transistors.
 9. The booster circuit of claim 7 wherein said switching circuit includes a transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said transistor.
 10. A booster circuit for use with a voltage regulator, having an output terminal coupled with a voltage bus, said voltage bus servicing a plurality of output blocks through a plurality of output lines, said booster circuit comprising: a plurality of switches for connecting each output line of the voltage bus to a voltage source; and a first switching circuit for sourcing additional current to the output terminal of the voltage regulator; and a second switching circuit for sourcing additional current to the output terminal of the voltage regulator.
 11. The booster circuit of claim 10 wherein said plurality of switches includes a plurality of transistors.
 12. The booster circuit of claim 10 wherein said first switching circuit includes a p-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said p-channel transistor and wherein said second switching circuit includes an n-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said n-channel transistor.
 13. A combination, comprising: a plurality of data pads; a plurality of output blocks each servicing one of said data pads; a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks; a plurality of switches for connecting each line of the voltage bus to a voltage source; and a switching circuit for sourcing additional current to the output terminal of the voltage regulator.
 14. The combination of claim 13 wherein said plurality of switches includes a plurality of transistors.
 15. The combination of claim 13 wherein said switching circuit includes a transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said transistor.
 16. A combination, comprising: a plurality of data pads; a plurality of output blocks each servicing one of said data pads; a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks; a plurality of switches for connecting each line of the voltage bus to a voltage source; a first switching circuit for sourcing additional current to the output terminal of the voltage regulator; and a second switching circuit for sourcing additional current to the output terminal of the voltage regulator.
 17. The combination of claim 16 wherein said plurality of switches includes a plurality of transistors.
 18. The combination of claim 16 wherein said first switching circuit includes a p-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said p-channel transistor and wherein said second switching circuit includes an n-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said n-channel transistor.
 19. A memory device, comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks; a plurality of switches for connecting each line of the voltage bus to a voltage source; and a switching circuit for sourcing additional current to an output terminal of said voltage regulator.
 20. The memory device of claim 19 wherein said plurality of switches includes a plurality of transistors.
 21. The memory device of claim 19 wherein said switching circuit includes a transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said transistor.
 22. A memory device, comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks; a plurality of switches for connecting each line of the voltage bus to a voltage source; a first switching circuit for sourcing additional current to the output terminal of the voltage regulator; and a second switching circuit for sourcing additional current to the output terminal of the voltage regulator.
 23. The memory device of claim 22 wherein said plurality of switches includes a plurality of transistors.
 24. The memory device of claim 22 wherein said first switching circuit includes a p-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said p-channel transistor and wherein said second switching circuit includes an n-channel transistor for sourcing current to the output terminal of the voltage regulator and a control portion responsive to a control pulse for controlling said n-channel transistor.
 25. A method of extending the duration of a control pulse, comprising: inputting the control pulse to a logic gate; delaying the control pulse by a plurality of delay periods to produce a plurality of delayed control pulses; and inputting said delayed control pulses to said logic gate, wherein a control pulse of extended duration is available at an output of said logic gate.
 26. A method of producing a control pulse of extended duration, comprising: inputting a plurality of signals to a first logic gate to produce a control pulse of a first duration; inputting the control pulse to a second logic gate; inputting the control pulse to a plurality of delay circuits to produce a plurality of control pulses having varying amounts of delay; and inputting said delayed control pulses to said second logic gate to produce a control pulse of extended duration.
 27. The method of claim 26 wherein said step of inputting a plurality of signals to a first logic gate includes the step of inputting a plurality of one-shot control pulses representative of demand.
 28. The method of claim 26 additionally comprising the step of using said control pulse of extended duration to control the period of conduction of a transistor.
 29. A circuit for producing a control pulse of extended duration, comprising: a first logic gate for receiving each of a plurality of signals and for producing a control pulse of a first duration; a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.
 30. A circuit for producing a control pulse of extended duration, said circuit for a voltage regulator having an output terminal coupled with a voltage bus, said voltage bus servicing a plurality of output blocks through a plurality of output lines, said circuit comprising: a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration; a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and; a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.
 31. A combination, comprising: a plurality of data pads; a plurality of output blocks each servicing one of said data pads; a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks; a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration; a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing a control pulse of extended duration, said control pulse input to said voltage regulator.
 32. A memory device, comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof; a transistor connected between a voltage source and the output terminal of said voltage regulator; and a circuit for producing a control pulse of extended duration for input to said transistor, said circuit comprising: a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration; a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.
 33. A memory device, comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage bus; a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof through said bus; a plurality of switches for connecting each line of the voltage bus to a voltage source; a switching circuit for sourcing additional current to an output terminal of said voltage regulator; and a circuit for producing a control pulse of extended duration for input to said switching circuit, said circuit comprising: a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration; a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.
 34. A memory device, comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage bus; a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof through said bus; a plurality of switches for connecting each line of the voltage bus to a voltage source; a first switching circuit including a p-channel device for sourcing additional current to an output terminal of said voltage regulator; a second switching circuit including an n-channel transistor for sourcing additional current to an output terminal of said voltage regulator; and a circuit for producing a control pulse of extended duration for input to said first and second switching circuits, said circuit comprising: a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration; a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.
 35. A method of forcing a voltage regulator of the type having an amplifier and an output transistor responsive to the amplifier into a low power mode, comprising: temporarily increasing the rate at which a bias current supplied to the differential amplifier is decreased; and pulling a load connected to the output transistor to a predetermined voltage other than ground.
 36. The method of claim 35 wherein said step of temporarily increasing includes the step of temporarily grounding through a diode the line carrying a signal for controlling the bias current.
 37. The method of claim 35 wherein said step of pulling to a predetermined voltage includes the step of pulling to a system voltage less the voltage drop across a diode.
 38. A method, comprising: controlling a pair of output transistors with a differential amplifier; temporarily increasing the rate at which a bias voltage is withdrawn from the differential amplifier; and pulling a node between a resistive and capacitive load connected to one of the transistors to a predetermined voltage other than ground.
 39. The method of claim 38 wherein said step of temporarily increasing includes the step of temporarily grounding through a diode the line carrying a signal for controlling the bias current.
 40. The method of claim 38 wherein said step of pulling to a predetermined voltage includes the step of pulling to a system voltage less the voltage drop across a diode.
 41. A method, comprising: controlling an output transistor with a signal produced by an amplifier; producing a control pulse; temporarily grounding a signal for controlling the bias voltage applied to the amplifier when the amplifier is to enter a low power mode of operation in response to said control pulse; and. pulling a node between a resistive and capacitive load connected to the transistor to a predetermined voltage other than ground in response to said control pulse.
 42. The method of claim 41 wherein said temporarily grounding and pulling steps are performed simultaneously.
 43. An apparatus for forcing a voltage regulator of the type having an amplifier controlling an output transistor into a low power mode, comprising: a first switch for connecting a control signal for controlling a source of bias voltage for the amplifier to ground; and a second switch connected between a resistive and capacitive load connected to the output transistor and a predetermined voltage other than ground.
 44. The apparatus of claim 43 wherein said second switch is connected to said predetermined voltage through a diode.
 45. A voltage regulator, comprising: first and second output transistors; an amplifier producing first and second output signals for controlling said first and second transistors, respectively; a resistive and capacitive load connected across said first output transistor; a circuit for providing a bias voltage to said amplifier in response to a control signal; a first switch for connecting said control signal to ground; and a second switch connected between said load and a predetermined voltage other than ground.
 46. A memory device, comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks, said voltage regulator comprising: first and second output transistors; an amplifier producing first and second output signals for controlling said first and second transistors, respectively; a resistive and capacitive load connected across said first output transistor; a circuit for providing a bias voltage to said amplifier in response to a control signal; a first switch for connecting said control signal to ground; and a second switch connected between said load and a predetermined voltage other than ground.
 47. A method of providing variable output drive capability to correct for output skews in subsequent amplification stages, comprising: providing a plurality of output drive stages; controlling the number of output drive stages that are activated in response to the amount of skew.
 48. The method of claim 47 wherein said step of controlling includes the step of generating a two-bit code and wherein said two-bit code is used to control the number of active output drive stages.
 49. A method of providing variable output drive capability, comprising: generating a two-bit signal representative of the relative strength of the n-channel and p-channel transistors in an output device; and controlling the number of output pre-driver stages that are active in response to said two-bit signal.
 50. A method, comprising: generating a signal representative of the relative strength of the n-channel and p-channel transistors in an output device; enabling certain output stages in a pre-driver in response to said signal; and inputting a high and a low data signal to the output device through the pre-driver.
 51. The method of claim 50 wherein said enabling step reduces skew in the data output by the output device.
 52. A pre-driver providing variable output drive capability, comprising: a plurality of output transistors; and a plurality of switches for controlling the conductivity of said plurality of output transistors in response to signals indicative of the strength of the output transistors in an output device.
 53. A pre-driver having an unbalanced output, comprising: a plurality of transistor output stages; and a plurality of switches for controlling the conductivity of said plurality of output stages in response to the level of conductivity of a subsequent output stage.
 54. A portion of a data path, comprising: an output driver responsive to a data signal; and a pre-driver providing variable output drive capability, comprising: a plurality of output transistors; and a plurality of switches for controlling the conductivity of said plurality of output transistors in response to signals indicative of the strength of output transistors in said output driver, said pre-driver for providing said data signal to said output driver.
 55. A memory device, comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including an output driver responsive to a data signal; and a pre-driver providing variable output drive capability, comprising: a plurality of output transistors; and a plurality of switches for controlling the conductivity of said plurality of output transistors in response to signals indicative of the strength of output transistors in said output driver, said pre-driver for providing said data signal to said output driver.
 56. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus; an output device coupled to the processor through the processor bus; a memory device coupled to the processor bus, the memory device comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks; a plurality of switches for connecting each line of the voltage bus to a voltage source; and a switching circuit for sourcing additional current to an output terminal of said voltage regulator.
 57. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus; an output device coupled to the processor through the processor bus; a memory device coupled to the processor bus, the memory device comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks; a plurality of switches for connecting each line of the voltage bus to a voltage source; a first switching circuit for sourcing additional current to the output terminal of the voltage regulator; and a second switching circuit for sourcing additional current to the output terminal of the voltage regulator.
 58. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus; an output device coupled to the processor through the processor bus; a memory device coupled to the processor bus, the memory device comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof; a transistor connected between a voltage source and the output terminal of said voltage regulator; and a circuit for producing a control pulse of extended duration for input to said transistor, said circuit comprising: a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration; a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.
 59. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus; an output device coupled to the processor through the processor bus; a memory device coupled to the processor bus, the memory device comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage bus; a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof through said bus; a plurality of switches for connecting each line of the voltage bus to a voltage source; a switching circuit for sourcing additional current to an output terminal of said voltage regulator; and a circuit for producing a control pulse of extended duration for input to said switching circuit, said circuit comprising: a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration; a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.
 60. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus; an output device coupled to the processor through the processor bus; a memory device coupled to the processor bus, the memory device comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage bus; a voltage regulator for providing voltage to said plurality of pads at an output terminal thereof through said bus; a plurality of switches for connecting each line of the voltage bus to a voltage source; a first switching circuit including a p-channel device for sourcing additional current to an output terminal of said voltage regulator; a second switching circuit including an n-channel transistor for sourcing additional current to an output terminal of said voltage regulator; and a circuit for producing a control pulse of extended duration for input to said first and second switching circuits, said circuit comprising: a first logic gate for receiving a plurality of signals each representative of the voltage demands of one of said plurality of output blocks and for producing a control pulse of a first duration; a plurality of delay circuits for receiving said control pulse and for producing a plurality of delayed control pulses; and a second logic gate for receiving said control pulse and said plurality of delayed control pulses and for producing the control pulse of extended duration.
 61. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus; an output device coupled to the processor through the processor bus; a memory device coupled to the processor bus, the memory device comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including a plurality of output blocks, each responsive to one of said data pads; a voltage regulator; a voltage bus for distributing voltage from said voltage regulator to said plurality of output blocks, said voltage regulator comprising: first and second output transistors; an amplifier producing first and second output signals for controlling said first and second transistors, respectively; a resistive and capacitive load connected across said first output transistor; a circuit for providing a bias voltage to said amplifier in response to a control signal; a first switch for connecting said control signal to ground; and a second switch connected between said load and a predetermined voltage other than ground.
 62. A computer system, comprising: a processor having a processor bus; an input device coupled to the processor through the processor bus; an output device coupled to the processor through the processor bus; a memory device coupled to the processor bus, the memory device comprising: a plurality of memory cells arranged in an array of rows and columns; a plurality of devices for identifying cells within said array; a plurality of pads; a data path connecting said plurality of pads and said array, said data path including: an output driver responsive to a data signal; and a pre-driver providing variable output drive capability, comprising: a plurality of output transistors; and a plurality of switches for controlling the conductivity of said plurality of output transistors in response to signals indicative of the strength of output transistors in said output driver, said pre-driver for providing said data signal to said output driver. 